Electronic microprocessor systems of the type wherein all the main electronic functions are integrated on a single integrated semiconductor chip wherein a small number of such chips are described in the following U.S. Patents, which are assigned to the assignee of this invention:
U.S. Pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "Calculator System Having An Exchange Data Memory Register", PA1 U.S. Pat. No. 3,934,233 issued to Roger J. Fisher and Jerald D. Rogers on Jan. 20, 1976 and entitled "Read-Only-Memory for Electronic Calculator", PA1 U.S. Pat. No. 3,931,507 issued to George L. Brantingham on Jan. 6, 1976 and entitled "Power-Up Clear in Electronic Digital Calculator", PA1 U.S. Pat. No. 3,988,604 issued to Joseph H. Raymond, Jr. on Oct. 26, 1976 and entitled "Electronic Calculator of Digital Processor Chip Having Multiple Function Arithmetic Unit Output".
The concepts of these prior applications have made possible vast reductions in the cost of the small personal-sized calculators. Continuing efforts to reduce the cost of these products include the development of a microprocessor chip utilizing minimum semiconductor chip area and which is capable of performing addition, subtraction, multiplication, division, squaring, square rooting, percent and memory operations. The chip disclosed herein may be utilized in hand-held or desk model calculators capable of performing operations of the aforementioned types and may be implemented on a very small semiconductor chip.
The present invention relates to a branch decoder system for a microprocessor and more specifically a branch decoder system for a microprocessor in an electronc calculator. An entire electronc calculator system which utilizes the branch decoder system of this invention is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, the invention is not limited to this type calculator, but rather may be utilized in microprocessors generally.
In the prior art, it has been known to use a single instruction branch operation, such as that disclosed in U.S. Pat. No. 3,931,507, where the entire branch address is incorporated as part of the branch instruction word. In that case, the instruction word must be longer than the branch address which, for reasons which will be explained, may result in uneconomic use of chip silicon area. Also, it has been known to use a relative addressing technique, such as that disclosed in U.S. Pat. No. 3,919,532; however, in that case, a branch can only be accomplished within a portion of that read-only-memory (ROM) by the execution of one branch instruction. Also, in the prior art, as exemplified by U.S. Pat. No. 3,988,604, it is been known to use both a program counter and a page address register to address a read-only-memory, the address in the program counter being changed by a branch instruction and the ROM page address being altered by a separate instruction. This technique, however, complicates the branch decoder logic.
It has been found that placing the branch address in the branch instruction word may make uneconomic use of the silicon area for implementing the microprocessor because the instruction word must be two or more bits longer than the instruction word address. For example, consider a ROM having provisions for storing 512 instruction words which uses a program counter having nine bit locations. Since it usually takes two or three additional bits to identify an instruction word as a branch instruction word and to provide for conditional branches, the outputted instruction word must have eleven or twelve bits. However, in relatively simple calculators, an eleven or twelve bit instruction word is longer than is required to decode the set of possible instructions. In the disclosed microprocessor system, a full set of instructions, including branch instructions, is decodeable using only a 9 bit instruction word. The branch system disclosed in U.S. Pat. Nos. 3,919,532 and 3,988,604 has certain disadvantages, in particular the instruction words of the branch system disclosed in these patents contain more than 9 bits and cannot be loaded directly into the program counter. This inability to load instruction words directly into the program counter complicates branching to all locations of the instruction memory. Further, these prior art systems may perform conditional branches but the condition tested is merely the state of a single preselected latch.
It was therefore one object of this invention to provide a branch logic system permitting more efficient use of chip silicon area in the instruction memory.
It is yet another object of this invention to provide a branch logic system wherein conditional branches may be made based on a state of a selected one of a plurality of latches.
It is still another object of this invention to provide an improved branch logic system for a microprocess or in an electronic calculator.
It is another object of this invention to equip an electronic microprocessor with a two cycle branch system.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, a branch logic system is provided on a semiconductor chip as part of an electronic calculator. The branch logic system includes branch decoder logic for decoding a branch instruction outputted from the system's instruction word memory during a given timing cycle and a circuit for altering the contents of the program counter addressing the instruction memory according to the instruction outputted from the instruction word memory during a timing cycle immediately following the given timing cycle. Further, the branch decoder logic is preferably responsive to a plurality of bits in the branch instruction word for conditioning the execution of the branch upon the state of a selected flag latch, the flag latch being selected according to the decoding of the aforementioned plurality of bits. Further, in a preferred embodiment, the number of bits in the instruction word outputted from the instruction memory equals the number of bits in the program counter used to address the instruction memory.